A number of communications standards are used in mainstream electronic devices, such as Universal Serial Bus (USB) 3.0, Frequency Modulation (FM), External Serial Advanced Technology Attachment (eSATA), and Peripheral Component Interconnect Express (PCIe). For many of these standards, requirements can limit the variance allowed with respect to bandwidth of device circuitry. For example, the PCIe standard limits the variation in loop bandwidth to 8 MHz to 16 MHz. In addition, these communications standards require limits on random jitter variation, as large jitter variations require designing circuits needing high power consumption.
For a closed loop system, the open loop gain determines a number of characteristics for that system, including loop bandwidth, and the open loop gain itself can depend on a number of factors, where gain is measured as a change in frequency for a unit change in current. For example, for an analog phase-locked loop (APLL) circuit 100 of FIG. 1, open loop gain depends on a gain of a current-controlled ring oscillator 130, response of a low pass filter 120, and current from a charge pump 115. The loop bandwidth of closed loop systems such as the APLL circuit 100 of FIG. 1 can sometimes fall outside the acceptable range for some applications, especially when process, voltage, and temperature variations in processing affect factors such as gain of oscillators, resistance of loop filters, and charge pump currents.
In particular, process, voltage, and temperature variations can affect the gain of oscillators. For example, these variations can affect the gain of the current-controlled ring oscillator 130 of FIG. 1, especially if the current-controlled ring oscillator 130 is operating in extreme conditions, such as in a strong process corner or weak process corner. The current-controlled ring oscillator 130 operates in a strong process corner if, due to fluctuations in silicon Gaussian distribution, transistors of the current-controlled ring oscillator 130 have a higher than normal drive strength, causing the current-controlled ring oscillator 130 to require a smaller voltage to operate at a normal frequency. Similarly, the current-controlled ring oscillator 130 operates in a weak process corner if, due to fluctuations in silicon Gaussian distribution, the transistors of oscillator 130 have a lower than normal drive strength, causing the current-controlled ring oscillator 130 to require a larger voltage to operate at a normal frequency. The current-controlled ring oscillator 130 operating in a strong process corner at a higher than normal frequency may show an increase in gain, with the gain further increasing if the current-controlled ring oscillator 130 is also operating in cold conditions. Likewise, the current-controlled ring oscillator 130 operating in a weak process corner at a lower than normal frequency may show a decrease in gain, with the gain further decreasing if the current-controlled ring oscillator 130 is also operating in hot conditions. Ultimately, the increases and decreases in gain of the current-controlled ring oscillator 130 due to the process, voltage, and temperature variations may lead to variance in the loop bandwidth of the APLL circuit 100 of FIG. 1. In addition, process, voltage, and temperature variations may affect phase-noise of the current-controlled ring-oscillator 130 in the APLL circuit 100.
In the APLL circuit 100 of FIG. 1, the frequency variations in an open loop of the current-controlled ring oscillator 130 are compensated in a closed loop via a feedback loop comprised of phase frequency detector 110, charge pump 115, and low pass filter 120. The feedback loop of the current-controlled ring oscillator 130 may not be able to compensate for the gain and phase-noise variations resulting from process, voltage, and temperature variations.